For example, metal oxide transistors [metal-oxide-semiconductor (field-effect transistors) or MOS(FETs)] are used within the technical field of electrically programmable storage cells.
In principle, a metal oxide transistor may be used as an electrically programmable fuse device, which does not interrupt, but instead produces an electrically conductive connection during programming (so-called antifuse technology).
For example, an n-channel MOS transistor has four terminals, namely a gate, source (n-doped), substrate (p-doped) and drain (n-doped). It should be noted accordingly that a parasitic npn bipolar transistor is formed from the source (emitter)-substrate (base)-drain (collector) fields (or regions).
If, during programming, the substrate voltage, i.e. the base voltage, is raised positively relative to the source voltage, i.e. the emitter voltage, charge carriers will be generated in the substrate region (base) across the pn junction between the substrate and the source; by applying a voltage at the drain being positive relative to the source, a current will flow which is generated in the substrate region by the charge carrier injection.
If the current between the source and the drain is selected to be sufficiently high, there will be local thermal heating between the source and the drain until local melting of the semiconductor material occurs; this local thermal heating is of such a magnitude that the semiconductor material melts; a permanent conducting channel is thus being established between the source and the drain, the conductivity of which is about 10,000 times greater than in the unprogrammed state.
An electrically programmable antifuse of this type is disclosed in the prior art, for example in publication U.S. Pat. No. 7,272,067 B1. As a result of the insulation layer arranged between the two p-type substrates in the form of a deep n-well, additional process steps are required, which complicates production of these known electrically programmable antifuses and incurs higher production costs.
In the electrically programmable antifuse according to publication U.S. Pat. No. 7,272,067 B1, the substrate potential is raised, relative to the source potential, to such an extent that a pn diode (with a forward voltage of about 0.6 volts) arranged between the substrate and the source allows a considerable current flow as a result of the polarity in the forward direction.
In this instance it has proven to be disadvantageous that no active circuits or active circuit parts can be operated during programming in the vicinity of the antifuse since, as result of the increased substrate potential, the function of active circuit(s)/circuit part(s) of this type is at least limited, or else they may even no longer be operational.
Alternatively or in addition, the prior art also poses the risk that a parasitic thyristor may be ignited by increasing the substrate potential (so-called latch-up effect or single event latch-up, SEL for short).
In this instance there is a malfunction in the electronic semiconductor component: an electrical short circuit of the supply voltage of the relevant component, which will generally lead to thermal destruction of the circuit if there are no safety measures.
For this reason, the prior art according to publication U.S. Pat. No. 7,272,067 B1 states that active circuit(s)/circuit part(s) in the same circuit arrangement (integrated circuits or ICs) must be arranged at a considerable distance from the antifuse, for example at a distance of about one hundred micrometers, thus resulting in a high area overhead that runs contrary to the general trend for miniaturising circuit arrangements.
Reference is also made to the following prior art                publication U.S. Pat. No. 6,650,143 B1, in which a programmable gate array is disclosed,        publication EP 1 777 708 A1, in which a non-volatile 3,5 transistor storage cell with gate oxide breakthrough is disclosed,        publication U.S. Pat. No. 7,280,425 B2, in which a one-time programmable antifuse cell is disclosed, and        publication US 2008/0007985 A1, in which an antifuse circuit with a biased transistor is disclosed.        